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smsc usb3500 datasheet revision 1.0 (06-05-08) datasheet product features usb3500 hi-speed usb host, device or otg phy with utmi+ interface ? usb-if ?hi-speed? certified to the universal serial bus specification rev 2.0 ? interface compliant with the utmi+ specification, revision 1.0. ? includes full support for the optional on-the-go (otg) protocol detailed in the on-the-go supplement revision 1.0a specification. ? functional as a host, device or otg phy. ? supports hs, fs, and ls data rates. ? supports fs pre-amble for fs hubs with a ls device attached (utmi+ level 3) ? supports hs sof and ls keep alive pulse. ? supports host negotiation protocol (hnp) and session request protocol (srp.) ? internal comparators support otg monitoring of vbus levels. ? low latency hi-speed rece iver (43 hi-speed clocks max) ? internal 1.8 volt regulator s allow operation from a single 3.3 volt supply ? internal short circuit protection of id, dp and dm lines to vbus or ground. ? integrated 24mhz crystal o scillator supports either crystal operation or 24mhz external clock input. ? internal pll for 480mhz hi-speed usb operation. ? supports usb 2.0 and legacy usb 1.1 devices ? 55ma unconfigured current (typical) - ideal for bus powered applications. ? 83ua suspend current (typical) - ideal for battery powered applications. ? full commercial operating temperature range from 0c to +70c ? 56 pin, qfn lead-free rohs compliant package (8 x 8 x 0.90 mm height)
order number: USB3500-ABZJ for 56 pin, qfn le ad-free rohs compliant package hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 2 smsc usb3500 datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2008 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 3 revision 1.0 (06-05-08) datasheet 0.1 reference documents ? universal serial bus specification, revision 2.0, april 27, 2000 ? usb 2.0 transceiver macrocell interface (utmi) specification, version 1.02, may 27, 2000 ? on-the-go supplement to the usb 2.0 spec ification, revision 1.0a, june 24, 2003 ? utmi+ specification, revisi on 1.0, february 2, 2004
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 4 smsc usb3500 datasheet table of contents 0.1 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 3 pin configuration and pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 usb3500 pin locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chapter 4 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 chapter 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 chapter 6 detailed functional de scription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 8bit bi-directional data bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 tx logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 rx logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 usb 2.0 transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.1 high speed and full speed transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.2 termination resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.3 bias generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 crystal oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 internal regulators and por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6.1 internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6.2 power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7 usb on-the-go (otg) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7.1 id detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7.2 vbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 chapter 7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2 opmodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3 test mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4 se0 handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.5 reset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6 suspend detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7 hs detection handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.8 hs detection handshake ? fs downstream facing port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.9 hs detection handshake ? hs downstream facing port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.10 hs detection handshake ? suspend timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.11 assertion of resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.12 detection of resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.13 hs device attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.14 usb reset and chirp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.15 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 chapter 8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 5 revision 1.0 (06-05-08) datasheet list of figures figure 1.1 basic utmi+ usb device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 1.2 utmi+ level 3 support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2.1 usb3500 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3.1 usb3500 pinout - top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6.1 fs clk relationship to transmit data and control signals . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6.2 fs clk relationship to receiv e data and control signals. . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6.3 transmit timing for a data packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6.4 receive timing for data with unst uffed bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6.5 receive timing for a handshake packet (no crc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6.6 receive timing for setup packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6.7 receive timing for data packet (with crc-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6.8 usb3500 on-the-go module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7.1 reset timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 7.2 suspend timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7.3 hs detection handshake timing behavior (fs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 7.4 chirp k-j-k-j-k-j sequence dete ction state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 7.5 hs detection handshake timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 7.6 hs detection handshake timing behavior from susp end . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 7.7 resume timing behavior (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 figure 7.8 device attach behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 7.9 usb reset and chirp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 7.10 usb3500 application diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8.1 USB3500-ABZJ 56 pin qfn package outline, 8 x 8 x 0.9 mm body (lead free) . . . . . . . . 46
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 6 smsc usb3500 datasheet list of tables table 3.1 usb3500 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4.1 maximum guaranteed ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4.3 recommended external clock conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5.1 dc electrical characteristics: su pply pins (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5.2 electrical characteristics: clkout start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 5.3 dc electrical characteristics: logic pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5.4 dc electrical characteristics: analog i/o pins (dp/dm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5.5 dynamic characteristics: analog i/o pins (dp/dm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5.6 dynamic characteristics: digital utmi pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5.7 otg electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5.8 regulator output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6.1 dp/dm termination vs. signaling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6.2 idgnd vs. usb cable type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7.1 device linestate states (dppd & dmpd = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7.2 host linestate states (dppd & dmpd = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7.3 operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7.4 usb 2.0 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7.5 reset timing values (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7.6 suspend timing values (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 7.7 hs detection handshake timing values (fs mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7.8 reset timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7.9 hs detection handshake timing values from suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 7.10 resume timing values (hs mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 7.11 attach and reset timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 8.1 56 terminal qfn package parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 7 revision 1.0 (06-05-08) datasheet chapter 1 general description the usb3500 is a stand-alone hi-speed usb physical layer transceiver (phy). the usb3500 uses a utmi+ interface to connect to an soc or fpga or custom asic. the usb3500 provides a flexible alternative to integrating the analog phy block for new designs. the usb3500 provides a fully compliant usb 2.0 interface, and supports high-speed (hs), full-speed (fs), and low-speed (ls) usb. the usb3500 supports all levels of the utmi+ specification as shown in figure 1.2 . the usb3500 can also, as an option, fully support the on-the-go (otg) protocol defined in the on- the-go supplement to the usb 2.0 specification. on-the-go allows th e link to dynamically configure the usb3500 as host or peripheral configured dynam ically by software. for example, a cell phone may connect to a computer as a peripheral to exchange address information or connect to a printer as a host to print pictures. finally the otg enabled device can connect to another otg enabled device to exchange information. all this is supported usin g a single low profile mini-ab usb connector. designs not needing otg can ignore the otg feature set. figure 1.1 basic utmi+ usb device block diagram soc/fpga/asic including device controller usb3500 usb 2.0 analog w/ otg usb connector (standard or mini) dm v bus dp id hi-speed usb app. utmi+ interface utmi+ digital logic utmi+ link
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 8 smsc usb3500 datasheet the usb3500 uses smsc?s advanced proprietary technology to minimize power dissipation, resulting in maximized battery life in portable applications. 1.1 applications the usb3500 is targeted for any application where a hi-speed usb connection is desired. the usb3500 is well suited for: ? cell phones ? mp3 players ? scanners ? printers ? external hard drives ? still and video cameras ? portable media players ? entertainment devices figure 1.2 utmi+ level 3 support utmi+ level 0 usb2.0 peripherals only added features usb3500 utmi+ level 3 usb2.0 peripheral, host controllers, on-the- go devices (hs, fs, ls, preamble packet) utmi+ level 2 usb2.0 peripheral, host controllers, on- the-go devices (hs, fs, and ls but no preamble packet) utmi+ level 1 usb2.0 peripheral, host controllers, and on-the-go devices (hs and fs only) usb3280 usb3250
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 9 revision 1.0 (06-05-08) datasheet chapter 2 functional overview the usb3500 is a highly integrated usb transceiver system. it contains a complete usb 2.0 phy with the utmi+ industry standard interface to support fast time to market fo r a usb controller. the usb3500 is composed of the functional blocks shown in figure 2.1 below. figure 2.1 usb3500 block diagram utmi+ digital otg module 24 mhz xtal internal regulators & por 5v power supply bias gen. xcvrsel[1:0] vdd3.3 xtal & pll xi vbus id vdd3.3 dp dm usb3500 vdd1.8 vdda1.8 m xo rbias mini-ab usb connector hs xcvr fs/ls xcvr resistors rpu_dp rpd_dm rpd_dp rpu_dm termsel txready suspendn txvalid reset chrgvbus rxactive opmode[1:0] id_dig idpullup clkout linestate[1:0] hostdisc dischrgvbus sessend data[7:0] rxvalid sessvld dppd dmpd rxerror vbusvld tx logic rx logic
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 10 smsc usb3500 datasheet chapter 3 pin configuration and pin definitions the usb3500 is offered in a 56 pin qfn package. the pin definitions and locations are documented below. 3.1 usb3500 pin locations the flag of the qfn package must be connected to ground with a via array. figure 3.1 usb3500 pinout - top view idpullup xcvrsel1 linestate[0] linestate[1] opmode[1] opmode[0] chrgvbus rxactive id_dig vss clkout vss vdd1.8 vdd3.3 sessvld data[1] data[0] data[2] data[3] data[4] data[5] data[6] data[7] rxvalid vss sessend dischrgvbus hostdisc rbias vdd3.3 vdd3.3 vdda1.8 xi xo vss vdd1.8 vbusvld vdd3.3 vss rxerror dmpd dppd vss dm dp vdd3.3 vss vdd3.3 reset txvalid suspendn id vbus txready termsel xcvrsel0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 29 30 31 32 34 35 36 37 38 39 40 33 48 47 46 45 44 43 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 usb3500 hi-speed usb utmi+ phy 56 pin qfn gnd flag
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 11 revision 1.0 (06-05-08) datasheet 3.2 pin definitions table 3.1 usb3500 pin definitions pin name direction, type active level description 1 vss ground n/a phy ground. 2 xcvrsel[0] input n/a transceiver select. these signals select between the fs and hs transceivers: transceiver select. 00: hs 01: fs 10: ls 11: ls data, fs rise/fall times 3 termsel input n/a termination select. this signal selects between the fs and hs terminations: 0: hs termination enabled 1: fs termination enabled 4 txready output high transmit data ready. if txvalid is asserted, the link must always have data available for clocking into the tx holding register on the rising edge of clkout. txready is an acknowledgement to the link that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. if txvalid is negated, txready can be ignored by the link. 5 vbus i/o, analog n/a vbus pin of the usb cable. 6 id input, analog n/a id pin of the usb cable. 7 suspendn input low suspend. places the transceiver in a mode that draws minimal power from supplies. in host mode, r pu is removed during suspend. in device mode, r pd is controlled by termsel. in suspend mode the clocks are off. 0: phy in suspend mode 1: phy in normal operation 8txvalid input high transmit valid. indicates that the data bus is valid for transmit. the assertion of txvalid initiates the transmission of sync on the usb bus. the negation of txvalid initiates eop on the usb. control inputs (opmode[1:0], termsel,xcversel) must not be changed on the de-assertion or assertion of txvalid. 9 reset input high reset. reset all state ma chines. after coming out of reset, must wait 5 rising edges of clock before asserting txvalid for transmit. assertion of reset: may be asynchronous to clkout de-assertion of reset: must be synchronous to clkout 10 vdd3.3 n/a n/a 3.3v phy supply. provides power for usb 2.0 transceiver, utmi+ digital, digital i/o, and regulators. 11 dp i/o, analog n/a d+ pin of the usb cable.
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 12 smsc usb3500 datasheet 12 dm i/o, analog n/a d- pin of the usb cable. 13 vss ground n/a phy ground. 14 vdd3.3 n/a n/a 3.3v phy supply. 15 xcvrsel[1] input n/a transceiver select. these signals select between the fs and hs transceivers: transceiver select. 00: hs 01: fs 10: ls 11: ls data, fs rise/fall times 16 chrgvbus input high charge vbus through a resistor to vdd3.3. 0: do not charge vbus 1: charge vbus 17 rxactive output high receive active. indi cates that the receive state machine has detected start of packet and is active. 18 opmode[1] input n/a operational mode. these signals select between the various operational modes: [1] [0] description 0 0 0: normal operation 0 1 1: non-driving (all terminations removed) 1 0 2: disable bit stuffing and nrzi encoding 1 1 3: reserved 19 opmode[0] input n/a 20 id_dig output high id digital. indicates the state of the id pin. 0: connected plug is a mini-a 1: connected plug is a mini-b 21 idpullup input high id pull-up. enables sampling of the analog id line. disabling the id line sampler will reduce phy power consumption. 0: disable sampling of id line. 1: enable sampling of id line. 22 vss ground n/a phy ground. 23 clkout output, cmos n/a 60mhz reference clock output. all utmi+ signals are driven synchronous to this clock. 24 vss ground n/a phy ground. 25 linestate[1] output n/a line state. these signals reflect the current state of the usb data bus in fs mode. bit [0] reflects the state of dp and bit [1] reflects the state of dm. when the device is suspended or resuming from a suspended state, the sign als are combinatorial. otherwise, the signals ar e synchronized to clkout. [1] [0] description 0 0 0: seo 0 1 1: j state 1 0 2: k state 1 1 3: se1 26 linestate[0] output n/a 27 vdd1.8 n/a n/a 1.8v regulator output for digital circuitry on chip. place a 0.1uf capacitor near this pin and connect the capacitor from this pin to ground. connect pin 27 to pin 49. table 3.1 usb3500 pin de finitions (continued) pin name direction, type active level description
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 13 revision 1.0 (06-05-08) datasheet 28 vdd3.3 n/a n/a 3.3v phy supply. provides power for usb 2.0 transceiver, utmi+ digital, digital i/o, and regulators. 29 hostdisc output high host disconnect. in hs host mode this indicates to that a downstream device has been disconnected. automatically reset to 0b when low power mode is entered. 30 dischrgvbus input high discharge vbus through a resistor to ground. 0: do not discharge vbus 1: discharge vbus 31 sessend output high session end. indicates that the voltage on vbus is below its b-device session end threshold. 0: vbus > v sessend 1: vbus < v sessend 32 data[7] i/o, cmos, pull-low n/a 8-bit bi-directional data bus. data[7] is the msb and data[0] is the lsb. 33 data[6] i/o, cmos, pull-low n/a 34 data[5] i/o, cmos, pull-low n/a 35 data[4] i/o, cmos, pull-low n/a 36 data[3] i/o, cmos, pull-low n/a 37 data[2] i/o, cmos, pull-low n/a 38 data[1] i/o, cmos, pull-low n/a 39 data[0] i/o, cmos, pull-low n/a 40 vss ground n/a phy ground. 41 rxvalid output high receive data valid. indicates that the data bus has received valid data. the receive data holding register is full and ready to be unloaded. the link is expected to register t he data bus on the next rising edge of clkout. 42 sessvld output high session valid. indicates that the voltage on vbus is above the indicated threshold. 0: vbus < v sessvld 1: vbus > v sessvld table 3.1 usb3500 pin de finitions (continued) pin name direction, type active level description
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 14 smsc usb3500 datasheet 43 dppd input n/a dp pull-down select. this signal enables the 15k ohm pull-down resistor on the dp line. 0: pull-down resistor not connected to dp 1: pull-down resistor connected to dp 44 dmpd input n/a dm pull-down select. this signal enables the 15k ohm pull-down resistor on the dm line. 0: pull-down resistor not connected to dm 1: pull-down resistor connected to dm 45 rxerror output high receive error. this output is clocked with the same timing as the receive data lines and can occur at anytime during a transfer. 0: indicates no error. 1: indicates a receive error has been detected. 46 vss ground n/a phy ground. 47 vbusvld output high vbus valid. indicates that the voltage on vbus is above the indicated threshold. 0: vbus < v vbusvld 1: vbus > v vbusvld 48 vdd3.3 n/a n/a 3.3v phy supply. provides power for usb 2.0 transceiver, utmi+ digital, digital i/o, and regulators. 49 vdd1.8 n/a n/a 1.8v regulator output for digital circuitry on chip. place a 4.7uf low esr capacitor near this pin and connect the capacitor from this pin to ground. connect pin 49 to pin 27. see section 6.6, "internal regulators and por," on page 27 . 50 vss ground n/a phy ground. 51 xo output, analog n/a crystal pin. if using an external clock on xi this pin should be floated. 52 xi input, analog n/a crystal pin. a 24mhz crystal is supported. the crystal is placed across xi and xo. an external 24mhz clock source may be driven into xi in place of a crystal. 53 vdda1.8 n/a n/a 1.8v regulator output for analog circuitry on chip. place a 0.1uf capacitor near this pin and connect the capacitor from this pin to ground. in parallel, place a 4.7uf low esr capacitor near this pin and connect the capacitor from this pin to ground. see section 6.6, "internal regulators and por" . 54 vdd3.3 n/a n/a 3.3v phy supply. provides power for usb 2.0 transceiver, utmi+ digital, digital i/o, and regulators. 55 vdd3.3 n/a n/a 3.3v phy supply. should be connected directly to pin 54. 56 rbias analog, cmos n/a external 1% bias resistor. requires a 12k ? resistor to ground. gnd flag ground n/a ground. the flag must be connected to the ground plane. table 3.1 usb3500 pin de finitions (continued) pin name direction, type active level description
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 15 revision 1.0 (06-05-08) datasheet chapter 4 limiting values note: stresses above those listed could cause damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. when powering this device from laboratory or system power supplies, it is im portant that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. table 4.1 maximum guaranteed ratings parameter symbol conditions min typ max units maximum vbus, id, dp, and dm voltage to ground v max_5v -0.5 +5.5 v maximum vdd1.8 and vdda1.8 voltage to ground v max_1.8v -0.5 2.5 v maximum 3.3v supply voltage to ground v max_3.3v -0.5 4.0 v maximum i/o voltage to ground v max_in -0.5 4.0 v operating temperature t max_op 070c storage temperature t max_stg -55 150 c table 4.2 recommended operating conditions parameter symbol conditions min typ max units 3.3v supply voltage v dd3.3 3.0 3.3 3.6 v input voltage on digital pins v i 0.0 v dd3.3 v input voltage on analog i/o pins (dp, dm) v i(i/o) 0.0 v dd3.3 v ambient temperature t a 0+70 o c table 4.3 recommended external clock conditions parameter symbol conditions min typ max units system clock frequency xi driven by the external clock; and no connection at xo 2 4 ( 100ppm ) mhz system clock duty cycle xi driv en by the external clock; and no connection at xo 45 50 55 %
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 16 smsc usb3500 datasheet chapter 5 electrical characteristics note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified. note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified. note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified. table 5.1 dc electrical characteristics: supply pins (note 1) parameter symbol conditi ons min typ max units unconfigured current i avg(ucfg) device unconfigured 55 ma fs idle current i avg(fs) fs idle not data transfer 55 ma fs transmit current i avg(fstx) fs current during data transmit 60.5 ma fs receive current i avg(fsrx) fs current during data receive 57.5 ma hs idle current i avg(hs) fs idle not data transfer 60.6 ma hs transmit current i avg(hstx) fs current during data transmit 62.4 ma hs receive current i avg(hsrx) fs current during data receive 61.5 ma low power mode i dd(lpm) vbus 15k ? pull-down and 1.5k ? pull-up resistor currents not included. 83 ua table 5.2 electrical characte ristics: clkout start-up parameter symbol conditions min typ max units suspend recovery time t start 2.25 3.5 ms table 5.3 dc electrical ch aracteristics: logic pins parameter symbol conditions min typ max units low-level input voltage v il v ss 0.8 v high-level input voltage v ih 2.0 v dd3.3 v low-level output voltage v ol i ol = 8ma 0.4 v high-level output voltage v oh i oh = -8ma v dd3.3 - 0.4 v input leakage current i li 10 ua pin capacitance cpin 4 pf
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 17 revision 1.0 (06-05-08) datasheet table 5.4 dc electrical characteri stics: analog i/o pins (dp/dm) parameter symbol conditi ons min typ max units fs functionality input levels differential receiver input sensitivity v difs | v(dp) - v(dm) | 0.2 v differential receiver common-mode voltage v cmfs 0.8 2.5 v single-ended receiver low level input voltage v ilse 0.8 v single-ended receiver high level input voltage v ihse 2.0 v single-ended receiver hysteresis v hysse 0.050 0.150 v output levels low level output voltage v fsol pull-up resistor on dp; r l = 1.5k ? to v dd3.3 0.3 v high level output voltage v fsoh pull-down resistor on dp, dm; r l = 15k ? to gnd 2.8 3.6 v termination driver output impedance for hs and fs z hsdrv steady state drive 40.5 45 49.5 ? input impedance z inp tx, rpu disabled 1.0 m ? pull-up resistor impedance z pu bus idle 0.900 1.24 1.575 k ? pull-up resistor impedance z purx device receiving 1.425 2.26 3.09 k ? pull-dn resistor impedance z pd 14.25 15.0 15.75 k ? hs functionality input levels hs differential input sensitivity v dihs | v(dp) - v(dm) | 100 mv hs data signaling common mode voltage range v cmhs -50 500 mv hs squelch detection threshold (differential) v hssq squelch threshold 100 mv un-squelch threshold 150 mv output levels hi-speed low level output voltage (dp/dm referenced to gnd) v hsol 45 ? load -10 10 mv
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 18 smsc usb3500 datasheet note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified. hi-speed high level output voltage (dp/dm referenced to gnd) v hsoh 45 ? load 360 440 mv hi-speed idle level output voltage (dp/dm referenced to gnd) v olhs 45 ? load -10 10 mv chirp-j output voltage (differential) v chirpj hs termination resistor disabled, pull-up resistor connected. 45 ? load. 700 1100 mv chirp-k output voltage (differential) v chirpk hs termination resistor disabled, pull-up resistor connected. 45 ? load. -900 -500 mv leakage current off-state leakage current i lz 10 ua port capacitance transceiver input capacitance c in pin to gnd 5 10 pf table 5.5 dynamic characteristics: analog i/o pins (dp/dm) parameter symbol condit ions min typ max units fs output driver timing rise time t fsr c l = 50pf; 10 to 90% of |v oh - v ol | 420ns fall time t fff c l = 50pf; 10 to 90% of |v oh - v ol | 420ns output signal crossover voltage v crs excluding the first transition from idle state 1.3 2.0 v differential rise/fall time matching frfm excluding the first transition from idle state 90 111.1 % hs output driver timing differential rise time t hsr 500 ps differential fall time t hsf 500 ps driver waveform requirements eye pattern of template 1 in usb 2.0 specification hi-speed mode timing receiver waveform requirements eye pattern of template 4 in usb 2.0 specification data source jitter and receiver jitter tolerance eye pattern of template 4 in usb 2.0 specification table 5.4 dc electrical characteristics: analog i/o pins (d p/dm) (continued) parameter symbol conditi ons min typ max units
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 19 revision 1.0 (06-05-08) datasheet note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified. note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified. table 5.6 dynamic characteri stics: digital utmi pins parameter symbol conditions min typ max units utmi timing data[7:0] t pd output delay. measured from phy output to the rising edge of clkout 25ns rxvalid rxactive rxerror linestate[1:0] txready data[7:0] t su setup time. measured from phy input to the rising edge of clkout. 51ns txvalid opmode[1:0] xcvrselect[1:0] termselect data[7:0] t h hold time. measured from the rising edge of clkout to the phy input signal edge. 0ns txvalid opmode[1:0] xcvrselect[1:0] termselect table 5.7 otg electrical characteristics parameter symbol conditions min typ max units sessend trip point v sessend 0.2 0.5 0.8 v sessvld trip point v sessvld 0.8 1.4 2.0 v vbusvld trip point v vbusvld 4.4 4.58 4.75 v vbus pull-up r vbuspu vbus to vdd3.3 (chrgvbus = 1) 281 340 ? vbus pull-down r vbuspd vbus to gnd (dischrgvbus = 1) 656 850 ? vbus impedance r vbus vbus to gnd 40 75 100 k ? id pull-up resistance r idpullup (idoullup = 1) 80 100 120 k ? id pull-up resistance r id (idpullup = 0) 1 m ?
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 20 smsc usb3500 datasheet note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified note: v dd3.3 = 3.0 to 3.6v; v ss = 0v; t a = 0c to +70c; unless otherwise specified table 5.8 regulator output voltages parameter symbol conditi ons min typ max units v dda1.8 v dda1.8 normal operation (suspendn = 1) 1.6 1.8 2.0 v v dda1.8 v dda1.8 low power mode (suspendn = 0) 0v v dd1.8 v dd1.8 1.6 1.8 2.0 v
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 21 revision 1.0 (06-05-08) datasheet chapter 6 detailed functional description figure 2.1 on page 9 shows the functional block diagram of the usb3500. each of the functions is described in detail below. 6.1 8bit bi-directional data bus operation the usb3500 supports an 8-bit bi-directional parallel interface. ? clkout runs at 60mhz ? the 8-bit data bus (data[7:0]) is used for transmit when txvalid = 1 ? the 8-bit data bus (data[7:0]) is used for receive when txvalid = 0 figure 6.1 shows the relationship between clkout and the transmit data transfer signals in fs mode. txready is only asserted for one clkout per byte time to signal the link that the data on the data lines has been read by the phy. the link may hold the data on the data lines for the duration of the byte time. transitions of txvalid must meet the defined setup and hold times relative to clkout. figure 6.2 shows the relationship between clkout and t he receive data control signals in fs mode. rxactive ?frames? a packet, transitioning only at the beginning and end of a packet. however transitions of rxvalid may take place an y time 8 bits of data are available. figure 6.2 also shows how rxvalid is only asserted for one clkout cycle per byte time even though the data may be presented for the full byte time. the xcvrselect signal determines whether the hs or fs timing relationship is applied to the data and control signals. figure 6.1 fs clk relationship to transmit data and control signals figure 6.2 fs clk relationship to receive data and control signals
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 22 smsc usb3500 datasheet 6.2 tx logic this block receives parallel data bytes placed on the data bus and performs the necessary transmit operations. these operations include parallel to serial conversion, bit stuffing and nrzi encoding. upon valid assertion of the proper tx control lines by the link and tx stat e machine, the tx logic block will synchronously shift, at either the fs or hs rate, the data to the fs/hs tx block to be transmitted on the usb cable. data transmit timing is shown in figure 6.3 . the behavior of the transmit state machine is described below. ? the link asserts txvalid to begin a transmission. ? after the link asserts txvalid it can assume th at the transmission has st arted when it detects txready has been asserted. ? the link must assume that the usb3500 has consumed a data byte if txready and txvalid are asserted on the rising edge of clkout. ? the link must have valid packet information (pid) asserted on the data bus coincident with the assertion of txvalid. ? txready is sampled by the link on the rising edge of clkout. ? the link negates txvalid to complete a packe t. once negated, the transmit logic will never reassert txready until after the eop has been generated. (txready will not re-assert until txvald asserts again.) ? the usb3500 is ready to transmit another packet imme diately. however, the link must conform to the minimum inter-p acket delays identified in the usb 2.0 specification. ? supports high speed disconnect detect through t he hostdisc pin. in host mode the usb3500 will sample the disconnect comparator at the 32nd bit of the 40 bit long eop during sof packets. ? supports fs pre-amble for fs hubs with a ls device. ? supports ls keep alive by receiving the sof pid. ? supports host mode resume k which ends with two low speed times of se0 followed by 1 fs ?j?. 6.3 rx logic this block receives serial data from the clock recove ry circuits and processes it to be transferred to the link on the data bus. the processing involved includes nrzi decoding, bit unstuffing, and serial to parallel conversion. upon valid assertion of the proper rx control lines, the rx logic block will provide bytes to the data bus as shown in the figu res below. the behavior of the receiver is described below. figure 6.3 transmit timing for a data packet
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 23 revision 1.0 (06-05-08) datasheet the assertion of reset will cause the usb3500 to deasserts rxactive and rxvalid. when the reset signal is deasserted the re ceive state machine starts look ing for a sync pattern on the usb. when a sync pattern is det ected, the receiver will assert rx active. the length of the received hi- speed sync pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end of five hubs. after valid serial data is received, the data is lo aded into the rx holding register on the rising edge of clkout, and rxvalid is asserted. the link mu st read the data bus on the next rising edge of clkout. in normal mode (opmode = 00), then stuffed bits are st ripped from the data stream. each time 8 stuffed bits are accumulated the usb 3500 will negate rxvalid for one clock cycle, thus skipping a byte time. when the eop is detected the usb3500 will ne gate rxactive and rxvalid. after the eop has been stripped, the usb3500 will begin looking for the next packet. the behavior of the usb3500 receiver is described below: ? rxactive and rxready are sampled on the rising edge of clkout. ? after a eop is complete the receiver will begin looking for sync. ? the usb3500 asserts rxactive when sync is detected. ? the usb3500 negates rxactive when an eop is de tected and the elasticity buffer is empty. ? when rxactive is asserted, rxvalid will be a sserted if the rx holding register is full. ? rxvalid will be negated if the rx holding regist er was not loaded during the previous byte time. this will occur if 8 stuffed bits have been accumulated. ? the link must be ready to consume a data byte if rxactive and rxvalid are asserted (rx data state). ? figure 6.5 shows the timing relationship between the received data (dp/dm), rxvalid, rxactive, rxerror and data signals. notes: ? figure 6.5 , figure 6.6 and figure 6.7 are timing examples of a hs/fs phy when it is in hs mode. when a hs/fs phy is in fs mo de there are approxim ately 40 clkout cycles every byte time. the receive state machine assumes that the link c aptures the data on the data bus if rxactive and rxvalid are asserted. in fs mode, rxvalid will only be asserted for one clkout per byte time. ? in figure 6.5 , figure 6.6 and figure 6.7 the sync pattern on dp/dm is shown as one byte long. the sync pattern received by a device can vary in length. these figures a ssume that all but the last 12 bits have been consumed by the hubs between the device and the host controller. figure 6.4 receive timing fo r data with unstuffed bits
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 24 smsc usb3500 datasheet figure 6.5 receive timing for a handshake packet (no crc) figure 6.6 receive timing for setup packet
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 25 revision 1.0 (06-05-08) datasheet 6.4 usb 2.0 transceiver the smsc hi-speed usb 2.0 transceiver consists of four blocks in the lower left corner of figure 2.1 on page 9 . these four blocks are labeled hs xcvr, fs/ls xcvr, resistors, and bias gen. 6.4.1 high speed and full speed transceivers the usb3500 transceiver meets all requ irements in the usb 2.0 specification. the receivers connect directly to the usb cable. th is block contains a separate differential receiver for hs and fs mode. depending on the mode, the se lected receiver provides the serial data stream through the multiplexer to the rx logic block. the fs mode section of the fs/hs rx block also consists of a single-ended receiver on each of the data lines to determine the correct fs linestate. for hs mode support, the fs/hs rx block contains a squelch circuit to insure that noise is never interpreted as data. the transmitters connect directly to the usb cable. the block contains a separate differential fs and hs transmitter which receive encoded, bit stuffed, serialized data from the tx logic block and transmit it on the usb cable. 6.4.2 termination resistors the usb3500 transceiver fully integrates all of th e usb termination resistors. the usb3500 includes two 1.5k ? pull-up resistors on dp and dm and a 15k ? pull-down resistor on both dp and dm. in addition the 45 ? high speed termination resistors are al so integrated. these integrated resistors require no tuning or trimming by the link. the stat e of the resistors is determined by the operating mode of the phy. the possible valid resistor combinations are shown in ta b l e 6 . 1 . the resistor settings signals shown in the table are internal to the usb3500. ? rpu_dp_en activates the 1.5k ? dp pull-up resistor ? rpu_dm_en activates the 1.5k ? dm pull-up resistor ? rpd_dp_en activates the 15k ? dp pull-down resistor ? rpd_dm_en activates the 15k ? dm pull-down resistor figure 6.7 receive timing for data packet (with crc-16)
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 26 smsc usb3500 datasheet ? hsterm_en activates the 45 ? dp and dm high speed termination resistors table 6.1 dp/dm termination vs. signaling mode signaling mode utmi+ interface setti ngs resistor settings xcvrsel[1:0] termsel opmode[1:0] dppd dmpd rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en general settings tri-state drivers xxb xb 01b xb xb 0b 0b 0b 0b 0b power-up or vbus < v sessend 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b host settings host chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b host hi-speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b host full speed x1b 1b 00b 1b 1b 0b 0b 1b 1b 0b host hs/fs suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b host hs/fs resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b host low speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host ls suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b host ls resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b host test j/test_k 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b peripheral settings peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral hs 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b peripheral fs 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b peripheral hs/fs resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b peripheral ls 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral ls suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b peripheral ls resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b peripheral test j/test k 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b otg device, peripheral chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b otg device, peripheral fs 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral hs/fs suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 27 revision 1.0 (06-05-08) datasheet 6.4.3 bias generator this block consists of an internal bandgap refe rence circuit used for generating the high speed driver currents and the biasing of the analog circuits. this block requires an external 12k , 1% tolerance, external reference resistor c onnected from rbias to ground. 6.5 crystal oscillator and pll the usb3500 uses an internal crystal driver and pll sub-system to provide a clean 480mhz reference clock that is used by the phy during both transmi t and receive. the usb3500 requires a clean 24mhz crystal or clock as a frequency reference. if the 24mhz reference is noisy or off frequency the phy may not operate correctly. the usb3500 can use either a crystal or an external clock oscillator for the 24mhz reference. the crystal is connected to the xi and xo pins as shown in the application diagram, figure 7.10 . if a clock oscillator is used, the clock should be connected to the xi input and the xo pin left floating. when using an external clock, the clock source must be clean so it does not degrade performance, and should be be driven with a 0 to 3.3 volt signal. after the 480mhz pll has locked to the correct fr equency, it will drive the clkout pin with a 60mhz clock. the usb3500 is guaranteed to start the clock within the time specified in ta b l e 5 . 2 . 6.6 internal regulators and por the usb3500 includes integrated power management functions to reduce the bill of materials and simplify product design. 6.6.1 internal regulators the usb3500 has two internal regulators that create two 1.8v outputs (labeled vdd1.8 and vdda1.8) from the 3.3 volt power supply input (vdd3.3). each regulator requires an external 4.7uf +/-20% low esr bypass capacitor to ensure stability. x5r or x7r ceramic capacitors are recommended since they exhibit an esr lower that 0.1ohm at frequencies greater than 10khz. the specific capacitor recommendations for each pin are detailed in table 3.1, "usb3500 pin locations" , and shown in figure 7.10, "usb3500 application diagram (top view)". note: the usb3500 regulators are designed to generate a 1.8volt supply for the usb3500 only. using the regulators to provide current for other circuits is not recommended and smsc does not guarantee usb performance or regulator stability in this case. otg device, peripheral hs/fs resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b otg device, peripheral test j/test k 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b table 6.1 dp/dm termination vs. signaling mode (continued) signaling mode utmi+ interface setti ngs resistor settings xcvrsel[1:0] termsel opmode[1:0] dppd dmpd rpu_dp_en rpu_dm_en rpd_dp_en rpd_dm_en hsterm_en
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 28 smsc usb3500 datasheet 6.6.2 power on reset (por) the usb3500 provides an internal por circuit that generates a reset pulse once the phy supplies are stable. the utmi+ digital can be re set at any time with the reset pin. 6.7 usb on-the-go (otg) module the usb3500 provides support for usb otg. this mode allows the usb3500 to be dynamically configured as a host or a device depending on the type of cable inserted into the mini-ab connector. when the mini-a plug of a cable is inserted into the mini-ab connector the usb device becomes the a-device. when a mini-b plug is inserted the device becomes the b-device. the otg a-device behaves similar to a host while the b-device behaves similar to a peripheral. the differences are covered in the otg supplement. the otg module meets all the requirements in the ?on-the-go supplement to the usb 2.0 specification?. in applicat ions where only host or device is required, the otg module is unused. the otg module can be broken in to 4 main blocks; id detection, vbus control, driving external vbus, and external vbus detection. each of thes e blocks is covered in the sections below. figure 6.8 usb3500 on-the-go module r=75k r>=656 r>=281 otg module vbus id vdd33 vbusvld sessvld sessend idpullup dischrgvbus id_dig chrgvbus 0.5v 1.4v 4.575v 0.6v r=100k r>1m
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 29 revision 1.0 (06-05-08) datasheet 6.7.1 id detection the usb3500 provides an id pin to determine th e type of usb cable connected. when the mini-a plug of a usb cable is inserted into the mini-ab connector, the id pin is shorted to ground. when the mini-b plug is inserted into the mini-ab c onnector, the id pin is allowed to float. the usb3500 provides an integrated pull-up resistor to pull the id pin to vdd3.3 when a mini-b plug is inserted and the cable is floating. when a mini-a plug is connected, the pull-up resistor will be overpowered and the id pin will be brought to ground. to save current when a mini-a plug is inserted, the id pull-up resistor can be disabled by cleari ng the idpullup pin. to prevent the id pin from floating to a random value, a weak pull-up resistor is provided at all times. the circuits related to the id comparator are shown in figure 6.8 and their related para meters are shown in ta b l e 5 . 7 . 6.7.2 vbus control the usb3500 includes all of the vbus comparators required for otg. the vbusvld, sessvld, and sessend comparators are fully integrated into t he usb3500. these comparators are used to ensure the vbus voltage is the correct value for proper usb operation. the vbusvld comparator is used by the link, when configured as an a device, to ensure that the vbus voltage on the cable is valid. the sessvld comparator is used by the link when configured as either an a or b device to indicate a session is requested or valid. finally the sessend comparator is used by the b-device to indicate a usb session has ended. also included in the vbus control block are the resistors used for vbus pulsing in srp. the resistors used for vbus pulsing include a pull-down to ground and a pull-up to vdd3.3. 6.7.2.1 sessend comparator the sessend comparator is designed to trip when vbus is less than 0.5 volts. when vbus goes below 0.5 volts, the session is considered to be ended and sessend will transition from 0 to 1. the sessend comparator is disabled when the suspendn = 0. when disabled, the sessend output is 0. the sessend comparator trip points are detailed in table 5.7 . 6.7.2.2 sessvld comparator the sessvld comparator is used when the phy is configured as either an a or b device. when configured as an a device, the sessvld is used to detect session request protocol (srp). when configured as a b device, sessvld is used to det ect the presence of vbus. the sessvld comparator is not disabled with suspendn and its output will alwa ys reflect the state of vbus. the sessvld comparator trip point is detailed in ta b l e 5 . 7 . note: the otg supplement specifies a voltage range for a-device session valid and b-device session valid comparator. the usb3500 phy combines the two comparators into one and uses the narrower threshold range. 6.7.2.3 vbusvld comparator the final vbus comparator is th e vbusvld comparator. this compar ator is only used when configured as an a-device. in the otg protocol the a-device is responsible to ensure that the vbus voltage is within a certain range. the vbusvld comparator is disabled when suspendn = 0. when disabled the vbusvld will read 0. the vbusvld comparator trip points are detailed in ta b l e 5 . 7 . table 6.2 idgnd vs. usb cable type usb plug otg role id voltage i d g nd ahost0 0 b peripheral 3.3 1
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 30 smsc usb3500 datasheet when the a-device is able to provide 8-100ma, it must ensure vbus doesn?t go below 4.4 volts. if the a-device can provide 100-500ma on vbus, it must en sure that vbus does not go below 4.75 volts. the internal vbus comparator is designed to ensure that vbus remains above 4.4 volts. if the design is required to supply over 100ma an external vbus comparator or overcurr ent fault detection should be used. 6.7.2.4 vbus pull-up an d pull-down resistors in addition to the internal vbus comparators, the usb3500 also includes the integrated vbus pull-up and pull-down resistors used for vbus pulsing. to discharge the vbus voltage, so that a session request can begin, the usb3500 provides a pull-down resistor from vbus to ground. this resistor is controlled by the dischrgvbus pin. the pull-up resistor is connected between vbus and vdd3.3. this resistor is used to pull vbus above 2.1 volts to indicate to the a-device that a usb session has been requested. the state of the pull-up resistor is controlled by the chrgvbu s pin. the pull-up and pull-down resistor values are detailed in ta b l e 5 . 7 . 6.7.2.5 vbus input impedance the otg supplement requires an a-device that su pports session request protocol to have an input impedance less than 100kohm and greater the 40kohm to ground. in addition, if configured as a b- device, the phy cannot draw more then 15 0ua from vbus. the usb3500 provides a 75k ? nominal resistance to ground which meets the above requirements.
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 31 revision 1.0 (06-05-08) datasheet chapter 7 application notes the following sections consist of se lect functional explanations to aid in implementing the usb3500 into a system. for complete description and specifications consult the usb 2.0 transceiver macrocell interface specification and universal serial bus specification revision 2.0. 7.1 linestate the voltage thresholds that the li nestate[1:0] signals use to reflec t the state of dp and dm depend on the state of xcvrselect. linestate[1:0] us es hs thresholds when the hs transceiver is enabled (xcvrselect = 0) and fs thresholds when the fs transceiver is enabled (xcvrselect = 1). there is not a concept of variable single-e nded thresholds in the usb 2.0 specification for hs mode. the hs receiver is used to detect chirp j or k, wher e the output of the hs receiver is always qualified with the squelch signal. if squelched, the output of the hs receiver is ignored. in the usb3500, as an alternative to using variable thresholds for the single-ended receivers, the following approach is used. in hs device mode, 3ms of no usb activity (idle state) signals a reset. the link monitors linestate[1:0] for the idle state. to minimize transitions on linestate[1:0] while in hs mode, the presence of !squelch is used to fo rce linestate[1:0] to a j state. table 7.1 device linestate states (dppd & dmpd = 0) state of dp/dm lines linestate[1:0] full speed xcvrselect[1:0]=01 termselect=1 high speed xcvrselect[1:0]=00 termselect=0 chirp mode xcvrselect[1:0]=00 termselect=1 ls[1] ls[0] 0 0 se0 squelch squelch 0 1 fs-j !squelch !squelch & hs differential receiver output 1 0 fs-k invalid !squelch & !hs differential receiver output 1 1 se1 invalid invalid table 7.2 host linestate states (dppd & dmpd = 1) state of dp/dm lines linestate[1:0] low speed xcvrsel[1:0]=10 termselect=1 full speed xcvrsel[1:0]=01 termselect=1 high speed xcvrsel[1:0]=00 termselect=0 opmode=00/01 chirp mode xcvrsel[1:0]=00 termselect=0 opmode=10 ls[1] ls[0] 0 0 se0 se0 squelch squelch 0 1 ls-k fs-j !squelch !squelch & hs differential receiver output 1 0 ls-j fs-k invalid !squelch & !hs differential receiver output
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 32 smsc usb3500 datasheet 7.2 opmodes the opmode[1:0] pins allow control of the operating modes. the opmode[1:0] signals are normally changed on ly when the transmitter and the receiver are quiescent, i.e. when entering a test mo de or for a device initiated resume. when using opmode[1:0] = 10, the sync and eop patterns are not transmitted. the only exception to this is when opmode[1:0] is set to 10 while txvalid has been asserted (the transceiver is transmitting a packet), in order to fl ag a transmission error. in this case, the usb3500 has already transmitted the sync pattern so upo n negation of txvalid the eop must also be transmitted to properly terminate the packet. changing the opmode[1:0] signals under all other conditions (while the transceiver is transmitting or receiving data) will generate undefined results. 7.3 test mode support 1 1 se1 se1 invalid invalid table 7.3 operational modes mode[1:0] state name description 00 normal operation transceiver operates with normal usb data encoding and decoding 01 non-driving allows the transceiver logic to support a soft disconnect feature which tri- states both the hs and fs transmitte rs, and removes any termination from the usb making it appear to an upst ream port that the device has been disconnected from the bus 10 disable bit stuffing and nrzi encoding disables bitstuffing and nrzi encoding logic so that 1's loaded from the data bus become 'j's on the dp/dm and 0's become 'k's 11 reserved n/a table 7.4 usb 2.0 test modes usb 2.0 test modes usb3500 setup operational mode link transmitted data xcvrselect & termselect se0_nak state 0 no transmit hs j state 2 all '1's hs k state 2 all '0's hs test_packet state 0 test packet data hs table 7.2 host linestate states (dppd & dmpd = 1) (continued) state of dp/dm lines linestate[1:0] low speed xcvrsel[1:0]=10 termselect=1 full speed xcvrsel[1:0]=01 termselect=1 high speed xcvrsel[1:0]=00 termselect=0 opmode=00/01 chirp mode xcvrsel[1:0]=00 termselect=0 opmode=10 ls[1] ls[0]
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 33 revision 1.0 (06-05-08) datasheet 7.4 se0 handling for fs operation, idle is a j state on the bus. se0 is used as part of the eop or to indicate reset. when asserted in an eop, se0 is never asserted for more than 2 bit times. the assertion of se0 for more than 2.5us is interpreted as a rese t by the device operating in fs mode. for hs operation, idle is a se0 state on the bus. se0 is also used to reset a hs device. a hs device cannot use the 2.5us asserti on of se0 (as defined for fs operation) to indicate reset since the bus is often in this state between packets. if no bus activity (idle) is detected for more than 3ms, a hs device must determine whether the downstream fa cing port is signaling a suspend or a reset. the following section details how this determination is made. if a reset is signaled, the hs device will then initiate the hs detection handshake protocol. 7.5 reset detection if a device in hs mode detects bu s inactivity for more than 3ms (t 1), it reverts to fs mode. this enables the fs pull-up on the dp line in an attempt to assert a continuous fs j state on the bus. the link must then check linestate for the se0 condi tion. if se0 is asserted at time t2, then the upstream port is forcing the reset state to the devi ce (i.e., a driven se0). the device will then initiate the hs detection handshake protocol. figure 7.1 reset timing behavior (hs mode) table 7.5 reset timing values (hs mode) timing parameter description value hs reset t0 bus activity ceases, signaling either a reset or a suspend. 0 (reference) t1 earliest time at which the device may place itself in fs mode after bus activity stops. hs reset t0 + 3. 0ms < t1 < hs reset t0 + 3.125ms t2 link samples linestate. if linestate = se0, then the se0 on the bus is due to a reset state. the device now enters the hs detection handshake protocol. t1 + 100s < t2 < t1 + 875s
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 34 smsc usb3500 datasheet 7.6 suspend detection if a hs device detects se0 asserted on the bus for more than 3ms (t1), it reverts to fs mode. this enables the fs pull-up on the dp line in an attempt to assert a continuous fs j state on the bus. the link must then check linestate for the j condition. if j is asserted at time t2, then the upstream port is asserting a soft se0 and the usb is in a j st ate indicating a suspend condition. by time t4 the device must be fully suspended. figure 7.2 suspend timing behavior (hs mode) table 7.6 suspend timing values (hs mode) timing parameter description value hs reset t0 end of last bus activity, signaling either a reset or a suspend. 0 (reference) t1 the time at which the device must place itself in fs mode after bus activity stops. hs reset t0 + 3. 0ms < t1 < hs reset t0 + 3.125ms t2 link samples linestate. if linestate = 'j', then the initial se0 on the bus (t0 - t1) had been due to a suspend state and the link remains in hs mode. t1 + 100 s < t2 < t1 + 875s t3 the earliest time where a device can issue resume signaling. hs reset t0 + 5ms t4 the latest time that a device must actually be suspended, drawing no more than the suspend current from the bus. hs reset t0 + 10ms
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 35 revision 1.0 (06-05-08) datasheet 7.7 hs detection handshake the downstream facing port asserting an se0 state on the bus initiates the hs detection handshake. there are three ways in which a device may enter the hs handshake detection process: 1. if the device is suspended and it detects an se0 state on the bus it may immediately enter the hs handshake detection process. 2. if the device is in fs mode and an se0 state is detected for more than 2.5s. it may enter the hs handshake detection process. 3. if the device is in hs mode and an se0 state is detected for more than 3.0ms. it may enter the hs handshake detection process. in hs mode, a de vice must first determine whether the se0 state is signaling a suspend or a reset condition. to do this the device reverts to fs mode by placing xcvrselect and termselect into fs mode. the device must not wait more than 3.125ms before the reversion to fs mode. after reverti ng to fs mode, no less than 100s and no more than 875s later the link must check the linestat e signals. if a j state is detected the device will enter a suspend state. if an se0 state is de tected, then the device wil l enter the hs handshake detection process. in each case, the assertion of the se0 state on t he bus initiates the reset. the minimum reset interval is 10ms. depending on the previous mode that the bus was in, the delay between the initial assertion of the se0 state and entering the hs ha ndshake detection can be from 0 to 4ms. this transceiver design pushes as much of the responsibility for timing events on to the link as possible, and the link requires a stable clkout sign al to perform accurate timing. in case 2 and 3 above, clkout has been running and is stable, however in case 1 the usb3500 is reset from a suspend state, and the internal oscilla tor and clocks of the transcei ver are assumed to be powered down. a device has up to 6ms after the release of suspendn to assert a minimum of a 1ms chirp k. 7.8 hs detection handshake ? fs downstream facing port upon entering the hs detection process (t0) , xcvrselect and termselect are in fs mode. the dp pull-up is asserted and the hs terminations are disabled. the link then sets opmode to disable bit stuffing and nrzi encoding , xcvrselect to hs mode, and begins the transmission of all 0's data, which asserts a hs k (chirp) on the bus (t1). the device chirp must last at least 1.0ms, and must end no later than 7.0ms after hs reset t0. at time t1 the device begins listening for a chirp sequence from the host port. if the downstream facing port is not hs capable, th en the hs k asserted by the device is ignored and the alternating sequence of hs chirp k?s and j?s is not generated. if no chir ps are detected (t4) by the device, it will enter fs mode by returning xcvrselect to fs mode.
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 36 smsc usb3500 datasheet notes: ? t0 may occur to 4ms after hs reset t0. ? the link must assert the chirp k for 66000 clkout cycles to ensure a 1ms minimum duration. figure 7.3 hs detection handshake timing behavior (fs mode) table 7.7 hs detection handshake timing values (fs mode) timing parameter description value t0 hs handshake begins. dp pull-up enabled, hs terminations disabled. 0 (reference) t1 device enables hs tran sceiver and asserts chirp k on the bus. t0 < t1 < hs reset t0 + 6.0ms t2 device removes chirp k from the bus. 1ms minimum width. t1 + 1.0 ms < t2 < hs reset t0 + 7.0ms t3 earliest time when downstream facing port may assert chirp kj sequence on the bus. t2 < t3 < t2+100s t4 chirp not detected by the device. device reverts to fs default state and waits for end of reset. t2 + 1.0ms < t4 < t2 + 2.5ms t5 earliest time at which host port may end reset hs reset t0 + 10ms
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 37 revision 1.0 (06-05-08) datasheet 7.9 hs detection handshake ? hs downstream facing port upon entering the hs detection process (t0) , xcvrselect and termselect are in fs mode. the dp pull-up is asserted and the hs terminations are disabled. the link then sets opmode to disable bit stuffing and nrzi encoding , xcvrselect to hs mode, and begins the transmission of all 0's data, which asserts a hs k (chirp) on the bus (t1). the device chirp must last at least 1.0ms, and must end no later than 7.0ms after hs reset t0. at time t1 the device begins listening for a chirp sequence from the downstream facing port. if the downs tream facing port is hs capable, then it will begin generating an alternating s equence of chirp k?s and chirp j?s (t3) after the termination of the chirp from the device (t2). after the device sees t he valid chirp sequence ch irp k-j-k-j-k-j (t6), it will enter hs mode by setting termselect to hs mode (t7). figure 7.4 provides a state diagram for chirp k-j-k-j-k-j validation. prior to the end of reset (t9) the device port must terminate the sequence of chirp k? s and chirp j?s (t8) and assert se0 (t8-t9). note that the sequence of chirp k?s and chirp j?s constitutes bus activity. the chirp k-j-k-j-k-j sequence occurs too slow to propagate through the serial data path, therefore linestate signal transitions must be used by the link to step through the chirp k-j-k-j-k-j state diagram, where ?k state? is equivalent to li nestate = k state and ?j state? is equivalent to linestate = j state. the link must employ a count er (chirp count) to count the number of chirp k and chirp j states. note that linestate does not fi lter the bus signals so the requirement that a bus state must be ?continuously asserted for 2.5s? mu st be verified by the link sampling the linestate signals. figure 7.4 chirp k-j-k-j-k-j se quence detection state diagram detect k? start chirp k-j-k-j-k-j detection inc chirp count k state !k detect j? inc chirp count j state !j chirp count != 6 & !se0 chirp count = 0 chirp count != 6 & !se0 chirp valid chirp invalid se0 chir p count
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 38 smsc usb3500 datasheet figure 7.5 hs detection handshake timing behavior (hs mode) table 7.8 reset timing values timing parameter description value t0 hs handshake begins. dp pull-up enabled, hs terminations disabled. 0 (reference) t1 device asserts chirp k on the bu s. t0 < t1 < hs reset t0 + 6.0ms t2 device removes chirp k from the bus. 1 ms minimum width. t0 + 1.0ms < t2 < hs reset t0 + 7.0ms t3 downstream facing port asserts chirp k on the bus. t2 < t3 < t2+100s t4 downstream facing port toggles chirp k to chirp j on the bus. t3 + 40s < t4 < t3 + 60s t5 downstream facing port toggles chirp j to chirp k on the bus. t4 + 40s < t5 < t4 + 60s t6 device detects downstream port chirp. t6 t7 chirp detected by the device. device removes dp pull-up and asserts hs terminations, reverts to hs default state and waits for end of reset. t6 < t7 < t6 + 500s t8 terminate host port chirp k-j sequence (repeating t4 and t5) t9 - 500s < t8 < t9 - 100s t9 the earliest time at which host port may end reset. the latest time, at whic h the device may remove the dp pull-up and assert the hs terminations, reverts to hs default state. hs reset t0 + 10ms
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 39 revision 1.0 (06-05-08) datasheet notes: ? t0 may be up to 4ms after hs reset t0. ? the link must use linestate to dete ct the downstream port chirp sequence. ? due to the assertion of the hs termination on t he host port and fs termination on the device port, between t1 and t7 the signaling levels on the bus are higher than hs signaling levels and are less than fs signaling levels. 7.10 hs detection handshake ? suspend timing if reset is entered from a suspende d state, the internal oscillator and clocks of the transceiver are assumed to be powered down. figure 7.6 shows how clkout is used to control the duration of the chirp generated by the device. when reset is entered from a suspended state (j to se0 transition reported by linestate), suspendn is combinatorially negated at time t0 by the link. it takes approximately 5 milliseconds for the transceiver's oscillator to stabilize. the device does not generate any transitions of the clkout signal until it is ?usable? (where ?usable? is defi ned as stable to within 10% of the nominal frequency and the duty cycle accuracy 505%). the first transition of clkout occurs at t1. the link then sets opmode to disable bit stuffing and nrzi encoding , xcvrselect to hs mode, and must asse rt a chirp k for 6 6000 clkout cycles to ensure a 1ms minimum duration. if clkout is 10% fast (66mhz) then chirp k will be 1.0ms. if clkout is 10% slow (54 mhz) then chirp k will be 1.2ms. the 5.6ms requirement for the first clkout transition after suspendn, ensures enough time to assert a 1ms chirp k and still complete before t3. once the chirp k is completed (t3) the link can begin looking for host chirps and use clkout to time the process. at this time, the device follows the same protocol as in section 7.9, "hs detection handshake ? hs downstream facing port" for completion of the high speed handshake. figure 7.6 hs detection handshake timing behavior from suspend clk60 look for host chirps device chirp k suspendn dp/dm termselect txvalid se0 j clk power up time xcvrselect opmode 1 opmode 0 time t0 t3 t4 t1 t2
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 40 smsc usb3500 datasheet to detect the assertion of the downstr eam chirp k's and chirp j's for 2.5us {t filt }, the link must see the appropriate linestate signals asserted cont inuously for 165 clkout cycles. 7.11 assertion of resume in this case, an event internal to the device initiates the resume process. a device with remote wake- up capability must wait for at least 5ms after the bus is in the idle state before sending the remote wake-up resume signaling. this allows the hubs to get into their suspend state and prepare for propagating resume signaling. the device has 10ms where it can draw a non-suspend current before it must drive resume signaling. at the beginning of this period the link may neg ate suspendn, allowing the transceiver (and its oscillator) to power up and stabilize. figure 7.7 illustrates the behavior of a device returning to hs mode after being suspended. at t4, a device that was previously in fs mode would maintain termselect and xcvrselect high. to generate resume signaling (fs 'k') the device is placed in the ?disable bit stuffing and nrzi encoding? operational mode (opmode [1:0] = 10), termselect and xcvrselect must be in fs mode, txvalid asserted, and all 0's data is presen ted on the data bus for at least 1ms (t1 - t2). table 7.9 hs detection handshake timing values from suspend timing parameter description value t0 while in suspend state an se0 is detected on the usb. hs handshake begins. d+ pull-up enabled, hs terminations disabled, suspendn negated. 0 (hs reset t0) t1 first transition of clkout. clkout ?usable? (frequency accurate to 10%, duty cyc le accurate to 505). t0 < t1 < t0 + 5.6ms t2 device asserts chirp k on the bus. t1 < t2 < t0 + 5.8ms t3 device removes chirp k from the bus. (1 ms minimum width) and begins looking for host chirps. t2 + 1.0 ms < t3 < t0 + 7.0 ms t4 clk ?nominal? (clkout is frequency accurate to 500 ppm, duty cycle accurate to 505). t1 < t3 < t0 + 20.0ms figure 7.7 resume timing behavior (hs mode)
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 41 revision 1.0 (06-05-08) datasheet 7.12 detection of resume resume signaling always takes place in fs mode (termselect and xcvrselect = fs enabled), so the behavior for a hs device is identical to that of a fs device. the link uses the linestate signals to determine when the usb transitions from the 'j' to the 'k' state and finally to the terminating fs eop (se0 for 1.25us-1.5s.). the resume signaling (fs 'k') will be asserted for at least 20ms. at the beginning of this period the link may negate suspendn, allowing the transceiver (a nd its oscillator) to power up and stabilize. the fs eop condition is relatively short. links that simply look for an se0 condition to exit suspend mode do not necessarily give the transceiver? s clock generator enough time to stabilize. it is recommended that all link implementations key off the 'j' to 'k' transition for exiting suspend mode (suspendn = 1). and within 1.25s after the trans ition to the se0 state (low-speed eop), the link must enable normal operation, i.e. enter hs or fs mode depending on the mode the device was in when it was suspended. if the device was in fs mode: then the link leav es the fs terminations enabled. after the se0 expires, the downstream port will assert a j state for one low-speed bit time, and the bus will enter a fs idle state (maintained by the fs terminations). if the device was in hs mode: then the link must s witch to the fs terminations before the se0 expires (< 1.25s). after the se0 expires, the bus will then enter a hs idle state (maintained by the hs terminations). 7.13 hs device attach figure 7.8 demonstrates the timing of the usb3500 control signals during a device attach event. when a hs device is attached to an upstream port, po wer is asserted to the device and the device sets xcvrselect and termselect to fs mode (time t1). v bus is the +5v power available on the usb cable. device reset in figure 7.8 indicates that v bus is within normal operational range as defined in the usb 2.0 specification. the assertion of device reset (t0) by the upstream port will initialize the device . by monitoring linestate, the link state machine knows to set the xcvrselect and term select signals to fs mode (t1). the standard fs technique of using a pull-up resistor on dp to signal the attach of a fs device is employed. the link must then check the linestat e signals for se0. if linestate = se0 is asserted table 7.10 resume timing values (hs mode) timing parameter description value t0 internal device event initiating the resume process 0 (reference) t1 device asserts fs 'k' on the bus to signal resume request to downstream port t0 < t1 < t0 + 10ms. t2 the device releases fs 'k' on the bus. however by this time the 'k' state is held by downstream port. t1 + 1.0ms < t2 < t1 + 15ms t3 downstream port asserts se0. t1 + 20ms t4 latest time at which a device, which was previously in hs mode, must restore hs mode after bus activity stops. t3 + 1.33s {2 low-speed bit times}
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 42 smsc usb3500 datasheet at time t2 then the upstream port is forcing the re set state to the device (i .e. driven se0). the device will then reset itself before initiating the hs detection handshake protocol. figure 7.8 device attach behavior table 7.11 attach and reset timing values timing parameter description value t0 vbus valid. 0 (reference) t1 maximum time from vbus valid to when the device must signal attach. t0 + 100ms < t1 t2 (hs reset t0) debounce interval. the device now enters the hs detection handshake protocol. t1 + 100ms < t2
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 43 revision 1.0 (06-05-08) datasheet 7.14 usb reset and chirp the usb 2.0 specification describes usb reset as a means of attaching a fs or a hs device to a host. this discussion will focus on a hs device connecting to a hs host. figure 7.9 shows the utmi+ interface for both a host (dppd & dmpd = 1) and a device (dppd & dmpd = 0). the following discussion applies to when the usb3500 is a configured as a device and is connected to another usb3500 configured as a host. since the host and device negotiate this transition, both are discussed together and the user may follow this discussion for either a host or device depending on the application of the usb3500. this sequence is also referred to as a ?high- speed chirp? due to the k-j pairs which the host sends to the downstream device. before the host begins a session, it will set xcvr select to fs mode (10b) and termselect to 1b to activate the hs termination. the host will also a sserted the 15kohm pull-down resistors on dp and dm. the 15kohm pull down resistors will pull dp and dm to 0 volts so that the host linestate will return single ended zero (se0) when nothing is attached. at time marker t0, the host link applies vbus to the downstream port. at t1, the device has detected a valid voltage on vbus and has asserted termselect to enable the 1.5k ohm pull-up resistor on dp. during t1 the host sees the linestate go from seo to a j due to the pull-up on dp. figure 7.9 usb reset and chirp xcvrselect termselect opmode txvalid data device dppd & dmpd == 0 host dppd & dmpd == 1 vbus xcvrselect termselect opmode txvalid linestate data t1 t0 t2 5volt se0 01 00 01 00 10 j se0 t3 t4 00h kseo t5 kjk j t6 t7 t8 k 00 ff ff 00 00 rxactive rxvalid 00 10 00 dp dm k-j pairs j 00 se0 00-ff hs sof a5h 00 hs sof packet hs sof packet 00h
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 44 smsc usb3500 datasheet note: note: should a device attached to the host be a ls device, then the 1.5 k ohm pull-up is applied to dm. the following discussion does not apply to a ls device attached. at t2, the host has detected the fs device attached to th e usb bus. at this time the host will reset the bus by driving a se0. the se0 is created by switching to hs mode and activating the hs termination by de-asserting termselect. the 45 ohm high speed terminations pull the bus to se0. at t3, the device will respond to the se0 by driv ing a ?device chirp k? onto the bus. the ?device chirp k? is driven with opmode = 10b so t hat bitstuffing and nrzi encoding is disabled. during t3 the hs host will see the ?device chirp k? and prepare to respond to the device by setting opmode = 10b to disable the bitstuffing and nrzi encoding. at t4, the device will stop driving a the chirp k, letting the bus return to se0, and wait for the host to respond. the device removes the k by de-assert ing txvalid. the device will have driven the k for a minimum of 1ms. the host sees the linestate change from k to se0. at t5, the host begins transmitting k-j pairs to the device. each k or j is 40-60us long and the k-j pairs are repeated for the remainder of the 10ms usb reset. at t6, the device has detected 3 k-j pairs. th e device switches the termselect low and changes opmode to 00b. the device is now in high speed an d waits for the first sof packet from the upstream host. when termselect is de-asserted, the hs termi nation is activated which lowers the amplitude of the k-j pairs. at t7, the host ends the k-j pairs and switches to normal hs mode by changing opmode to 00b. at t8, the host sends the first sof packet. this is done by putting the sof pid 0xa5 on the data bus and asserting txvalid. the link transfers the sof packet. after, the sof packet a normal high speed usb session started.
hi-speed usb host, device or otg phy with utmi+ interface datasheet smsc usb3500 45 revision 1.0 (06-05-08) datasheet 7.15 application diagram figure 7.10 usb3500 application diagram (top view) usb connector (standard or mini) utmi+ interface to link 5 volt supply 12k vdd3.3 3.3 volt supply 4.7uf 0.1uf 1m 24mhz c load id rbias vdd3.3 33 c load 4.7uf vdd3.3 c vbus host only 4.7uf 0.1uf c vbus host device otg device min 100uf 1uf 1uf max 10uf 6.5uf idpullup xcvrsel1 linestate[0] linestate[1] opmode[1] opmode[0] chrgvbus rxactive id_dig clkout vdd1.8 vdd3.3 sessvld data[1] data[0] data[2] data[3] data[4] data[5] data[6] data[7] rxvalid sessend dischrgvbus hostdisc vdda1.8 xi xo vdd1.8 vbusvld vdd3.3 rxerror dmpd dppd dm dp vdd3.3 vdd3.3 vbus txready termsel xcvrsel0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 29 30 31 32 34 35 36 37 38 39 40 33 48 47 46 45 44 43 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 usb3500 hi-speed usb utmi+ phy 56 pin qfn gnd flag reset txvalid suspendn id dm dp vbus 0.1uf
hi-speed usb host, device or otg phy with utmi+ interface datasheet revision 1.0 (06-05-08) 46 smsc usb3500 datasheet chapter 8 package outline the usb3500 is offered in a compact 56 lead qfn package. notes: 1. controlling unit: millimeter. 2. dimension b applies to plated terminals and is measured between 0.15mm and 0.30mm from the terminal tip. tolerance on the true position of the leads is 0.05 mm at maximum material conditions (mmc). 3. details of terminal #1 identifier are optional but must be located within the zone indicated. figure 8.1 USB3500-ABZJ 56 pin qfn package outline, 8 x 8 x 0.9 mm body (lead free) table 8.1 56 terminal qfn package parameters min nominal max remarks a 0.70 ~ 1.00 overall package height a1 0 0.02 0.05 standoff a2 0.60 ~ 0.90 mold thickness a3 0.20 ref copper lead-frame substrate d 7.85 8.00 8.15 x overall size d1 7.55 ~ 7.95 x mold cap size d2 2.25 4.5 6.80 x exposed pad size e 7.85 8.00 8.15 y overall size e1 7.55 ~ 7.95 y mold cap size e2 2.25 4.5 6.80 y exposed pad size l 0.30 ~ 0.55 terminal length e 0.50 basic terminal pitch b 0.18 ~ 0.30 terminal width

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